• 2024: All news updated here: https://www.microsoft.com/en-us/research/people/eschouks/
  • 2023
    • Published my work on LLM inference efficiency using phase splitting: Splitwise at https://aka.ms/splitwise
    • Nominated as co-chair for Hot Carbon 2024
    • Served as publication chair for MICRO 2023
    • Published my work on power oversubscription of LLM clusters: POLCA (https://aka.ms/POLCA)
    • Served on ISCA 2023 Industry track PC
  • 2022
    • ​Served on the PC for HPCA 2022, ISCA 2022, MICRO 2022, ASPLOS 2023. 
  • 2021
    • June: Invited panelist for the "Undergrads in Computer Architecture" panel at ISCA 2021.
    • June: Invited panelist for the MLADS 2020 conference panel on Sustainable ML
    • April: Served on the Program Committee for ICPP 2021.
    • April: Served as the Co-Chair for Special Sessions and Tutorials at ICCD 2021.
    • January: Served on the Program Committee for ISCA 2021.
  • 2020
    • November: Invited panelist for the MLADS 2020 conference panel on Sustainable ML.
    • November: Served as External Reviewer for HPCA 2020.
    • November: Served on the Program Committee for HPCA 2020 Industry track.
    • October: Invited panelist on the JOBS panel at MICRO 2020.
    • September: Served on the Program Committee for ICCD 2020 for the computer architecture track.
    • September: ​Served on the Program Committee for MICRO 2020.
    • ​June:     Presented my paper on "Buddy Compression: Enabling larger HPC and DL workloads on GPUs" at the International Symposium on Computer Architecture (ISCA 2020), conducted online due to the shelter in place. (link)
    • January: Served on the external review committee for ISCA 2020.
  • 2019
    • December 18: Invited talk on my research at the Indian Institute of Science (IISc), Bangalore, India.
    • December 9:   Organized a Microsoft-ASPLOS PC workshop to inform the research community of the latest topics we are working on here at Microsoft.
    • April 11:           Invited talk on my research for webinar series by Women in Computer Architecture [link]
    • March 21:        Media coverage of my work in hpcwire [link]
    • Feb 21:              Invited talk on "A systems perspective on compression in deep learning" at SiFive's RISC-V Revolution Symposium in Austin, TX.​
    • Jan 7-31:            Candidate talks at Intel Labs (Santa Clara, California and Hillsboro, Oregon offices), AMD Research (Austin Office) and ARM Research (Austin Office) on "Efficient Hardware Main Memory Compression".
  • 2018
    • ​October 24:     Presented my paper "Compresso: Pragmatic Main Memory Compression [pdf]" at the 51st IEEE MICRO (International Symposium on Microarchitecture) in Fukuoka, Japan.
    • July 24:            Invited talk at Intel Labs on "OS-Transparent Main Memory Compression".
    • July 6:              Invited poster at the Accelerated Compute Research Summit at Google Mountainview, on my work on Main Memory Compression.
  • 2017
    • ​March 27:       Poster at NVMW (Non-Volatile Memories Workshop) San Diego, about "Improving non-volatile main memory with on-chip DRAM"
  • 2016
    • December 6:  Presented at the Annual Intel Strategic Research Alliance (ISRA) workshop for low latency architectures at Intel, Hillsboro, OR.